Generally, bit lines in a memory array experience current leakage. Depending on applications, a bit line may be coupled to many bit cells (e.g., 64, 128, 256, etc., cells). When a cell is activated (e.g., turned on for reading) current may leak in other cells even though transistors in those cells have been deactivated (e.g., turned off). If, for example, a bit line is coupled to 64 memory cells, and only one cell is accessed for reading, current can leak through 63 transistors in the other 63 memory cells. The more the memory cells are coupled to a bit line, the higher the amount of current is leaked.
An approach uses leakage tracking in a bias circuit to compensate for the bit-line cell leakage. In this approach, however, the tracking cell in the worst case can be over-compensated and may cause a reading low failure when current in the tracking cell is heavily leaked. Further, leakage compensation does not work well when the current leaks heavily.
High current leakage seems to get worse due to the continued lower program voltage (e.g., 1.8V versus 2.5V) in OTP (one time programming) memory, metal fuses that replace poly fuses, expanded memory macro density, eFuse (electrical fuse) being used in high leakage processes such as G and HP, reduction of channel length to reduce the memory cell die area, etc.
Like reference symbols in the various drawings indicate like elements.